(1) Field of the Invention
The present invention relates to a process used to create a crown shaped capacitor structure, for high density dynamic random access memory, (DRAM), circuits.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve semiconductor device performance, while still attempting to reduce the manufacturing costs of these semiconductor devices. These objectives have been in part realized by the ability of the semiconductor industry to fabricate semiconductor memory chips, using sub-micron features. The use of sub-micron features, or micro-miniaturization, results in reductions of performance degrading capacitances and resistances. In addition the use of smaller features result in a smaller chip, however still possessing the same level of integration obtained for larger semiconductor chips, fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of sub-micron features however, in some areas, can adversely influence the performance of a DRAM device. The DRAM device is usually comprised of a stacked capacitor, (STC), structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance, and thus the performance of STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 256 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area, available for the placement of an overlying STC structure.
One method of maintaining, or increasing STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of a capacitor structure, featuring a crown shaped storage node structure, comprised of vertical features of silicon, connected to a horizontal silicon feature, with the horizontal silicon feature, overlying and contacting, the top surface of a storage node contact plug, which in turn contacts a source region of an underlying transfer gate transistor. The increased surface area, presented by the vertical features of the crown shaped structure, results in an increase in capacitance, without increasing the lateral dimensions of the capacitor structure. The crown shaped storage node structure can be formed by initially forming a capacitor opening, in an insulator layer, followed by the deposition and patterning of a polysilicon layer, creating a polysilicon, crown shaped storage node structure, located on the exposed surfaces of the capacitor opening. The procedure of forming a capacitor opening, in an insulator layer, is accomplished overlying a second insulator layer, with the capacitor opening procedure, having to selectively stop, or end point, on the second insulator layer. Attack, or removal of second insulator layer, during the capacitor opening procedure, can not be tolerated since the second insulator layer is used to protect underlying elements of the DRAM cell.
This invention will describe a novel process sequence for creating a crown shaped storage node structure, for a DRAM device, featuring the use of a silicon oxynitride, (SiO.sub.x N.sub.y) layer, used as the stop layer, at the conclusion of the capacitor opening procedure, with the SiO.sub.x N.sub.y layer overlying, and protecting the underlying insulator layers that are used for the passivation of specific DRAM cell elements. Prior art, such as Walker, in U.S. Pat. No. 5,518,948, describes the use of a silicon nitride stop layer, used in the capacitor fabrication sequence. However the use of silicon oxynitride offers several advantages over the prior art, such as: an improved anti-reflective coating, (ARC), during the photolithographic portion of the capacitor node contact opening procedure; improved endpoint detection, at the conclusion of the capacitor opening procedure; reduced stress in the BPSG layer, reducing the possibility of film cracks on the BPSG layer; a diffusion barrier for the crown shaped storage node structure from underlying doped insulator layer; and reduced loading phenomena, during the dry etching procedure, used for the capacitor opening.